// Copyright (C) 1953-2020 NUDT
// Verilog module name - ts_injection_schedule 
// Version: TIS_V1.0
// Created:
//         by - fenglin 
//         at - 10.2020
////////////////////////////////////////////////////////////////////////////
// Description:
//         injection schedule of time-sensitive packet
//             - parse command;
//             - use a true dual port ram to cache injection slot table; 
//             - schedule descriptor of time-sensitive packet according to injection slot table;
//             - top module.
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps
 
module st_injection_schedule
#(
parameter clk_period = 24'h080000//8ns
)
(
        i_clk                          ,
        i_rst_n                        ,
                                       
        iv_addr                        ,         
        iv_wdata                       ,         
        i_wr                           ,      
        i_rd                           ,                      
        o_wr                           ,      
        ov_addr                        ,      
        ov_rdata                       ,   
                                       
        i_st_rxenable                  ,       
        i_cycle_start                     ,
        iv_time_slot_length            ,
                                       
        i_ts_injection_addr_ack        ,
        ov_ts_injection_addr           ,
        o_ts_injection_addr_wr         ,
                                          
        ism_state                      ,
        iv_injection_slot_table_period       
);

// I/O
// clk & rst
input                  i_clk;
input                  i_rst_n;

input       [18:0]     iv_addr;                         
input       [31:0]     iv_wdata;                        
input                  i_wr;         
input                  i_rd;         

output                 o_wr            ;          
output      [18:0]     ov_addr         ;       
output      [31:0]     ov_rdata        ;
//configuration finish and time synchronization finish
input                  i_st_rxenable; 
// calculation of time slot
input                  i_cycle_start;      
input      [10:0]      iv_time_slot_length;    // measure:us
// result of schedule
output     [4:0]       ov_ts_injection_addr;
output                 o_ts_injection_addr_wr;
input                  i_ts_injection_addr_ack; 

output     [2:0]       ism_state; 

input      [10:0]      iv_injection_slot_table_period;

wire       [9:0]       wv_time_slot;
wire                   w_time_slot_switch;

wire       [9:0]       wv_ram_addr_tic2ram     ;   
wire       [19:0]      wv_ram_wdata_tic2ram    ;  
wire                   w_ram_wr_tic2ram        ;   
wire       [19:0]      wv_ram_rdata_ram2tic    ;  
wire                   w_ram_rd_tic2ram        ;

command_parse_and_encapsulate_sis command_parse_and_encapsulate_sis_inst(
.i_clk                    (i_clk                ),                
.i_rst_n                  (i_rst_n              ),      
                                                
.iv_addr                  (iv_addr              ),         
.iv_wdata                 (iv_wdata             ),         
.i_wr                     (i_wr                 ),      
.i_rd                     (i_rd                 ),      
                                                
.o_wr                     (o_wr                 ),      
.ov_addr                  (ov_addr              ),      
.ov_rdata                 (ov_rdata             ),      

.ov_ram_addr              (wv_ram_addr_tic2ram  ),      
.ov_ram_wdata             (wv_ram_wdata_tic2ram ),      
.o_ram_wr                 (w_ram_wr_tic2ram     ),         
.iv_ram_rdata             (wv_ram_rdata_ram2tic ),      
.o_ram_rd                 (w_ram_rd_tic2ram     )             
);

time_slot_calculation 
#(
.clk_period(clk_period)
)
injection_time_calculation_inst(
.i_clk              (i_clk                         ),
.i_rst_n            (i_rst_n                       ),
                                                   
.i_cycle_start      (i_cycle_start                 ),
.iv_time_slot_length(iv_time_slot_length           ),

.iv_slot_period     (iv_injection_slot_table_period),

.ov_time_slot       (wv_time_slot      ),
.o_time_slot_switch (w_time_slot_switch)
);

injection_schedule_module injection_schedule_module_inst(
.i_clk                        (i_clk               ),
.i_rst_n                      (i_rst_n             ),
.i_st_rxenable                (i_st_rxenable       ),
.iv_time_slot                 (wv_time_slot        ),
.i_time_slot_switch           (w_time_slot_switch  ),

.iv_injection_slot_table_wdata(wv_ram_wdata_tic2ram),
.i_injection_slot_table_wr    (w_ram_wr_tic2ram    ),
.iv_injection_slot_table_addr (wv_ram_addr_tic2ram ),
.ov_injection_slot_table_rdata(wv_ram_rdata_ram2tic),
.i_injection_slot_table_rd    (w_ram_rd_tic2ram    ),

.i_ts_injection_addr_ack      (i_ts_injection_addr_ack),
.ov_ts_injection_addr         (ov_ts_injection_addr   ),
.o_ts_injection_addr_wr       (o_ts_injection_addr_wr ),

.ism_state                    (ism_state)  
);
endmodule